1. Field of the Invention
The present invention generally relates to an interconnection structure of a semiconductor device and a manufacturing method thereof and, more particularly, to an interconnection structure of a semiconductor integrated circuit device in which each of multilayer aluminum interconnection layers is connected through connection holes and a manufacturing method thereof.
2. Description of the Background Art
In a semiconductor device, elements such as transistors are usually formed on a semiconductor substrate. A variety of interconnections are formed on the semiconductor substrate in order to connect electrically these elements or an element and an external circuit. A polycrystal silicon film, refractory metal film, refractory metal silicide film, aluminum film, aluminum alloy film, etc. have been used as these interconnections. It has been necessary to decrease interconnection resistance in recent semiconductor integrated circuit devices with high degree of integration in order to achieve a high speed operation. Therefore, a structure of aluminum multi-layer interconnections formed of aluminum films or aluminum alloy films having small specific resistance is indispensable for a semiconductor integrated circuit device.
FIG. 20 is a partial plan view showing one example of a structure of aluminum multi-layer interconnections in a conventional semiconductor integrated circuit device. FIG. 21 is a partial sectional view showing a cross section taken along line XX1--XX1 of FIG. 20.
Referring to these views, a p type well 2 and an n type well 3 are formed in a p type silicon substrate 1. An n type MOS transistor 8 is formed in a p type well 2. A p type MOS transistor 9 is formed in an n type well 3. N type MOS transistor 8 includes n type impurity regions 81, 82 as a pair of source/drain regions and a gate electrode 7 formed therebetween. P type MOS transistor 9 includes p type impurity regions 91, 92 as a pair of source/drain regions and a gate electrode 7 formed therebetween. In order to isolate n type MOS transistor 8 and p type MOS transistor 9 electrically from each other, an isolation oxide film 5 is formed therebetween. An inversion preventing region 4 of p type impurity region is formed under isolation oxide film 5.
First aluminum interconnection layers 1A are formed to be connected with each of n type impurity regions 81, 82 and p type impurity regions 91, 92 through contact holes formed in a silicon oxide film 10. Referring to FIG. 20, a first aluminum interconnection layer 1A connects with n type impurity regions 81 through a contact hole C2. A first aluminum interconnection layer 1A connects with p type impurity region 91 through a contact hole C5. A first aluminum interconnection layer 1A connects with n type impurity region 82 through a contact hole C3 and connects with p type impurity region 92 through a contact hole C4. A first aluminum interconnection layer 1A connects with a gate electrode 7 through a contact hole C1.
A first aluminum interconnection layer 1A includes a barrier metal layer 11, an aluminum alloy layer 12 and an upper metal layer 130. A conventional example of a structure of the first aluminum interconnection layer 1A is disclosed in Japanese Patent Laying-Open No. 64-80065. According to the disclosure, barrier metal layer 11 is formed of MoSi.sub.x having a film thickness of about 100-200.ANG.. Aluminum alloy layer 12 is formed of Al-Cu-Si alloy having a film thickness of 4000-6000.ANG.. Upper metal layer 130 is formed of MoSi.sub.x having a film thickness of about 100-1000.ANG..
A second aluminum interconnection layer 2A (15) connects with a first aluminum interconnection layer 1A through a through-hole T (19). An interlayer insulating film 14 is formed between first aluminum interconnection layer 1A and second aluminum interconnection layer 2A. A passivation film 16 is formed on second aluminum interconnection layer 2A.
A method of forming the interconnection structure shown in FIG. 21 will be described. FIGS. 22 through 32 are partial sectional views showing a sectional structure in respective steps of a manufacturing method of a conventional interconnection structure.
Referring to FIG. 22, p type well 2 and n type well 3 are formed in p type silicon substrate 1. In order to isolate the element forming regions electrically from each other, an isolation oxide film 5 of thick silicon oxide and thereunder an inversion preventing region 4 of p type impurities are formed. N type MOS transistor 8 including n type impurity regions 81, 82 as a pair of source/drain regions is formed in the element forming region of p type well 2. P type MOS transistor 9 including p type impurity regions 91, 92 as a pair of source/drain regions is formed in the element forming region of n type well 3. Silicon oxide film 10 is formed having contact holes through which each surface of n type impurity regions 81, 82 and p type impurity regions 91, 92 is exposed.
As shown in FIG. 23, barrier metal layer 11 including refractory metal is formed to connect with each of n type impurity regions 81, 82 and p type impurity regions 91, 92 using a reactive sputtering method. Aluminum alloy layer 12 is formed on barrier metal layer 11 using the sputtering method. Upper metal layers 130 including refractory metal is formed on aluminum alloy layer 12 using the sputtering method.
Referring to FIG. 24, a photoresist film 17 is formed on upper metal layer 130. Only predetermined regions 17a are subjected to exposure, as indicated by the allows, so as to pattern photoresist film 17.
As shown in FIG. 25, photoresist film 17 undergoes development and only exposed portions 17a are selectively removed.
Referring to FIG. 26, upper metal layer 130, aluminum alloy layer 12 and barrier metal layer 11 are selectively etched away by reactive ion etching using photoresist film 17 as a mask.
As shown in FIG. 27, interlayer insulating film 14 is formed on the whole surface.
As shown in FIG. 28, a photoresist film 18 is formed on interlayer insulating film 14. Only a predetermined region 18a is subjected to exposure, as indicated by the arrows, so as to pattern photoresist film 18.
As shown in FIG. 29, photoresist film 18 undergoes development and exposed portion 18a is selectively removed.
As shown in FIG. 30, through-hole 19 is formed by selectively removing interlayer insulating film 14 using photoresist film 18 as a mask.
As shown in FIG. 31, second aluminum interconnection layer 15 is formed to contact a surface of upper metal layer 130 through through-hole 19.
Finally, referring to FIG. 32, passivation film 16 is formed to cover a surface of second aluminum interconnection layer 15.
In the above described interconnection structure, as first aluminum interconnection layer 1A, a combination including refractory metal 11, aluminum alloy layer 12 and upper metal layer 130 is use. Barrier metal layer 11 is used in such a structure of aluminum interconnection layers for the following reasons.
(i) If aluminum directly contacts a silicon substrate (impurity-diffused-region) in a contact portion, abnormal reaction (alloy spike) is locally caused. The reacted layer then penetrates the impurity-diffused-region and extends below the silicon substrate. As a result, junction leakage of the impurity-diffused-region is caused. In order to prevent the leakage, the barrier metal layer is formed to contact directly the silicon substrate (the impurity-diffused-region).
(ii) Silicon in an aluminum alloy layer deposits in a contact portion because of solid phase epitaxial growth, so that poor contact is caused. In order to prevent it, the barrier metal layer is formed under the aluminum alloy layer.
The reasons for forming upper metal layer 130 including refractory metal on aluminum alloy layer 12 are as follows.
(a) In order to remove a first aluminum interconnection layer selectively, or to form a through-hole reaching a surface of the first aluminum interconnection layer, a photoresist film is formed on the first aluminum interconnection layer. Photoresist film is then subjected to exposure selectively. Light incident on the photoresist film reaches the surface of the first aluminum interconnection layer. If the uppermost portion of the first aluminum interconnection layer is formed of aluminum alloy layer, light penetrated the photoresist film reflects on the surface of the aluminum alloy layer. The reflected light enlarges the exposed region of the photoresist film. The enlargement causes errors in pattern dimensions of the photoresist film.
FIG. 33 is a sectional view showing a problem when the photoresist film formed on the first aluminum interconnection layer is exposed in order to be selectively removed. The first aluminum interconnection layer is formed of barrier metal layer 11 and aluminum alloy layer 12. Photoresist film 17 is formed on aluminum alloy layer 12. Light is directed onto a predetermined exposed region 17a (indicated by dotted lines), as indicated by the arrows, in the patterning of photoresist film 17. The incident light reflects on the surface of aluminum alloy layer 12 as indicated by the arrow and is directed also to a region 17b (indicated by a two-dotted line) other than predetermined exposed region 17a. Thus, the reflected light enlarges the exposed portion of photoresist film 17, so that errors are caused in dimensions of a finished resist pattern.
FIG. 34 is a sectional view showing a problem when a photoresist film formed on a first aluminum interconnection layer is exposed to form a through-hole reaching a surface of the first aluminum interconnection layer. Interlayer insulating film 14 is formed on aluminum alloy layer 12 which is the uppermost portion of the first aluminum interconnection layer. In order to form the through-hole in interlayer insulating film 14, that is, in order to remove interlayer insulating film 14 selectively, photoresist film 18 is formed. Light is directed only to a predetermined exposed region 18a of photoresist film 18, as indicated by the arrows. The incident light passes through photoresist film 18 and also reaches a surface of aluminum alloy layer 12. The light reflected on the surface of aluminum alloy layer 12 is directed not only to a predetermined exposed region 18a (indicated by dotted lines), but also to a region 18b (indicated by a two-dotted line). Consequently, the exposed portion of photoresist film 18 is increased and errors are caused in dimensions of the completed resist pattern.
Upper metal layer 130 is formed on aluminum alloy layer 12 in order to solve these problems. That is, upper metal layer 130 including refractory metal is formed on aluminum alloy layer 12 so as to reduce light reflected on a surface of a first aluminum interconnection layer when a photoresist film is subjected to exposure. The manufacturing steps corresponding to FIGS. 33 and 34, respectively, are shown in FIGS. 24 and 28.
(b) If the upper portion of a first aluminum interconnection layer is formed of an aluminum alloy layer, a protrusion (hillock) of aluminum grows in solid phase from a surface of the aluminum alloy layer by heat treatment etc. in the succeeding step where a silicon oxide film and a photoresist are formed on the first aluminum interconnection layer.
FIG. 35 is a partial sectional view showing a problem when a hillock is formed. Aluminum alloy layer 12 is formed on the uppermost portion of the first aluminum interconnection layer. Interlayer insulating film 14 of a silicon oxide film etc. is formed on the aluminum alloy layer 12. Patterned photoresist film 18 is formed so as to form a through-hole in interlayer insulating film 14. By heat treatment in a step of forming interlayer insulating film 14 and photoresist film 18, a hillock 12a is formed on a surface of aluminum alloy layer 12. A protrusion 14a is formed, resulting from the hillock, in interlayer insulating film 14, so that photoresist film 18 formed on protrusion 14a is thinner than photoresist film 18 on other regions. As a result, if etching process is performed using photoresist film 18 as a mask, not only a predetermined region 14b to be etched away but also protrusion region 14c of interlayer insulating film 14 is etched away. Hillock 12a of aluminum alloy layer 12, which is the uppermost portion of the first aluminum interconnection layer is then exposed and problem arises that hillock 12a is short-circuited with a second aluminum interconnection layer formed thereon.
In order to solve such problems, photoresist film 18 is formed thick, and also upper metal layer 130 including refractory metal is formed as the uppermost portion of the first aluminum interconnection layer. The manufacturing step corresponding to FIG. 35 when upper metal layer 130 including refractory metal is formed on aluminum alloy layer 12 is shown in FIG. 29.
(c) An interlayer insulating film and a passivation film are formed on a first aluminum interconnection layer. The first aluminum interconnection layer is sometimes cut off by film stress of these upper insulating films. An upper metal layer containing refractory metal is formed on an aluminum alloy layer so as to enhance resistance to such a stress migration phenomenon. The upper metal layer is also formed on the aluminum alloy layer in order to prevent the whole first aluminum interconnection layer from being cut off when the aluminum alloy layer forming the main portion of the first aluminum interconnection layer is damaged by electromigration. Electromigration is a phenomena in which metallic atoms move when electron current of high density collides with metallic atoms of interconnections and scatters. Through the effect of the electromigration, a damage of the interconnection layer called void is caused along a grain boundary. The void gradually grows and current density increases with decreasing cross section of the interconnection layer, resulting in heat generation and disconnection.
(d) If the uppermost portion of a first aluminum interconnection layer is formed of an aluminum alloy layer, a problem arises that it is difficult to remove residues, reaction products, etc. produced in the formation of a through-hole.
FIG. 36 is a sectional view showing a problem when a through-hole exposing a surface of the first aluminum interconnection layer is formed. Through-hole 19 is formed in interlayer insulating film 14 to expose a surface of aluminum alloy layer 12 as the uppermost portion of the first aluminum interconnection layer. In the forming of through-hole 19, residues 20a from the etching step remain on the sidewall of through-hole 19. Residues 20a still remain after a photoresist film formed on interlayer insulating film 14 is removed by ashing. Denatured particles 20b etc. are formed on the bottom surface of through-hole 19, that is, an exposed surface of aluminum alloy layer 12. It is necessary to perform cleaning process so as to remove these residues 20a and denatured particles 20b and to stabilize the interface of the first aluminum interconnection layer and second aluminum interconnection layer in through-hole 19. However, it is difficult to perform the cleaning process by wet chemical process using a solution of acid or alkali. That is because the exposed surface of aluminum alloy layer 12 through through-hole 19 is corroded by the solution of acid or alkali. In order to perform the cleaning process sufficiently by wet chemical process, upper metal layer 13 including refractory metal is formed on aluminum alloy layer 12 as the uppermost portion of the first aluminum interconnection layer.
(e) For the above reasons (a)-(d), an upper metal layer containing refractory metal is formed on the uppermost portion of a first aluminum interconnection layer. However, in a region of a through-hole, aluminum alloy layer 12 forming the first aluminum interconnection layer and second aluminum interconnection layer 15 are connected with upper metal layer 130 interposed. As a result, compared to a structure without upper metal layer 130, a resistance value of a through-hole is larger in such an interconnection structure. For example, when an upper metal layer containing refractory metal of specific resistance of 100.times.10.sup.-6 .OMEGA..multidot.cm is formed in a thickness of 0.1 .mu.m, a resistance value of a 0.8 by 0.8 .mu.m through-hole connection increases by about 0.2.OMEGA. and it is about two to four times that of a through-hole when an upper metal layer including a refractory metal is not interposed. There are also some cases in which upper metal layer 130 including refractory metal and aluminum alloy layer 12 react and a new alloy layer is formed in heat treatment at 400.degree.-500.degree. C. performed when interlayer insulating layer 14 is formed. For example, when upper metal layer 130 including Ti is formed, refraction of aluminum and titanium proceeds and a resistance value of a through-hole significantly increases.
As described above, even if the above described requirements (a)-(d) are fulfilled when an upper metal layer containing refractory metal is used as the uppermost portion of first aluminum interconnection layer, there is a problem that a resistance value of a through-hole connection is increased. As a result, if, for example, the above-stated interconnection structure is used for a device operating at a high speed, a resistance value of a through-hole connection is increased and thus there is a possibility that the operating speed of the device decreases. In Japanese Patent Laying-Open No. 64-80065, a structure is disclosed in which an upper metal layer of MoSi.sub.x is formed as the uppermost portion of a first aluminum interconnection layer; however, it does not disclose an interconnection structure in which the effect described in the above (a)-(d) are achieved and an increase of a resistance value of a through-hole connection is suppressed.